1. Field of Invention
This invention relates to digital circuits. Specifically, the present invention relates to programmable digital filters for use in telecommunications systems.
2. Description of the Related Art
Digital filters are used in a variety of demanding applications ranging from electronic control systems to cellular telecommunications systems. Such applications often require programmable digital filters that consume minimal power.
Digital filter programmability and low power consumption are particularly important in digital cellular telecommunications systems such as code division multiple access (CDMA) systems. A typical CDMA cellular telecommunications system is characterized by a plurality of mobile transceivers in communication with one or more base stations. Signals transmitted by the mobile transceivers are received by a base station and often relayed to a mobile switching center (MSC). The MSC in turn routes the signal to another base station, a public switched telephone network (PSTN) or to another mobile transceiver. Similarly, the public switched telephone network may transmit a signal to a mobile unit via a base station and a mobile switching center.
It is often advantageous to employ different sampling rates within the mobile transceiver, base station, and/or MSC. To accommodate different sampling rates, digital filters located within the mobile transceiver, base station, and/or MSC are often programmable. Filter programmability also reduces the need to replace expensive hardware when mobile transceiver specifications change.
In a typical programmable digital filter, several registers or delay circuits are connected in series. The outputs of the registers are connected to parallel programmable gain circuits having gains related to filter transfer function coefficients. The outputs of the gain circuits are input to multipliers connected in series. The filter design often requires many expensive digital multipliers that consume excess power and occupy valuable circuit board space. The digital multipliers result in large filter power consumption and decreased mobile transceiver battery life.
Hence a need exists in the art for a space-efficient low-power programmable digital filter that can accommodate a range of input frequencies or sample rates. There is a further need for a power-efficient transceiver incorporating a low-power programmable digital filter.
The need in the art is addressed by the programmable digital filter of the present invention. In the illustrative embodiment, the inventive filter is adapted for use with a transceiver and includes a first finite impulse response filter section for receiving an input signal. The first finite impulse response filter section has a first transfer function. An infinite impulse response filter section is connected to the first finite impulse response filter section and has a second transfer function. A second finite impulse response filter section is connected to the infinite impulse response filter section and outputs a filtered output signal in response the receipt of the input signal by the programmable digital filter. The second finite impulse response filter section has a third transfer function. A programmable coefficient is provided in the first, second, and/or the third transfer functions.
In a specific embodiment, the first transfer function has a first programmable coefficient. The second transfer function has a second programmable coefficient and the third transfer function has a third programmable coefficient. The programmable digital filter further includes a processor for providing a control signal. A memory provides the first, second, and/or third programmable coefficients in response to the control signal. A high-pass filter section provides input to the first finite impulse response filter section. A multiplexer selectively bypasses the high-pass filter in response to a bypass control signal from the processor. The processor generates the bypass control signal in response to DC offsets, i.e., biases occurring in the input signal.
In the illustrative embodiment, the first finite impulse response filter section includes a first jammer filter, a second jammer filter, and a third jammer filter for removing telecommunications jammer signals in the input signal. The first, second, and third jammer filters have first, second, and third jammer filter transfer functions with the first programmable coefficient, a fourth programmable coefficient, and a fifth programmable coefficient, respectively. The finite impulse response filter section further includes a first bit truncation circuit, a second bit truncation circuit, and a third bit truncation circuit at the outputs of the first, second and third jammer filters, respectively. In one exemplary embodiment of the invention the first, second, and third bit truncation circuits remove three most significant bits and three least significant bits from an input code word. The first bit truncation circuit is connected in series at an output of the first jammer filter. The second bit truncation circuit is connected in series between the first jammer filter and the second jammer filter. The third bit truncation circuit is connected in series between the second jammer filter and the third jammer filter.
The infinite impulse response filter section includes a first equalization filter and a second equalization filter. An input of the first equalization filter is connected to an output of the first finite impulse response filter section. The first equalization filter has two programmable coefficients and the second equalization filter has one programmable coefficient. A bias and gain correction circuit removes any bias in the output signal and adjusts the gain of the output signal.
The bias and gain correction circuit includes a subtractor for subtracting a bias from the output signal and providing an offset-compensated signal in response thereto. The bias and gain correction circuit removes a predetermined number of least significant bits from a code word in the offset-compensated signal and providing a bit-corrected signal in response thereto. The bias and gain correction circuit further includes a multiplier for multiplying the bit-corrected signal by a predetermined factor and providing a gain-adjusted signal in response thereto. The bias and gain correction circuit removes a first predetermined number of least significant bits and a second predetermined number of most significant bits from a code word in the gain-adjusted signal and provides a programmable digital output filter output signal in response thereto.
In the illustrative embodiment, the programmable digital filter is implemented in a telecommunications system receiver that includes an antenna for receiving a radio signal having a first frequency. A mixer mixes the radio signal to an intermediate frequency signal. A delta-sigma analog-to-digital converter converts the intermediate frequency signal to a digital intermediate frequency signal. A digital filter includes the programmable digital filter and converts the digital intermediate frequency signal to a digital baseband signal characterized by a (chip rate)*8 sample rate. A baseband processor processes the digital baseband signal at the chip rate.
The novel design of the present invention is facilitated by the separation of functionality of the programmable digital filter into various sections such as the infinite impulse response filter sections and the finite impulse response filter sections. By separating filter functionality into several blocks and providing strategic programmable coefficients for each block, control over the composite transfer function of the programmable digital filter is maximized while minimizing power consumption of the programmable digital filter.